1. Field of the Invention
The present invention relates to a non-volatile memory. More particularly, the present invention relates to a non-volatile memory structure including a charge-trapping layer, and to an operating method and a fabricating method of the same.
2. Description of the Related Art
Recently, trapping-type non-volatile memory was discussed widely for allowing a simplified fabricating process and possibly having more than one data storage sites per cell. For example, Eitan et al. (IEEE EDL 2000, Vol. 21, No. 11, pages 543-545) described a localized trapping 2-bit non-volatile memory cell, which has a MOS-type structure with an n-doped gate and an ONO composite layer between the substrate and the gate, wherein the nitride layer serves as a charge-trapping layer. However, since the channel length of the memory cell is short, serious punch-through leakage and second-bit effect are caused.
Moreover, the article in IEEE NVSM 2003 (pages 42-43) discloses a U-shaped non-volatile memory cell that also has an n-doped gate and an ONO composite layer, wherein the channel length is increased by the trench so that the short channel issues are overcome. The article also teaches to erase the memory cell through band-to-band hot hole tunneling (BTBHHT) from the substrate to the nitride trapping layer. However, BTBHHT from the substrate might cause tunnel oxide damage and result charge loss.